1. Field of the Invention
The present invention relates to semiconductor integrated circuits and methods for integrated circuit manufacture. More particularly, the present invention relates to a test reticle and alignment mark optimization method for precision alignment of various integrated circuit process layers.
2. Description of Related Art
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coat, etching, and deposition. In many of these steps, material is overlayed or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical. The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy. If the proper alignment tolerance is not achieved, a large number of device defects can result.
A waferstepper is typically used to align a semiconductor wafer during the various process steps. The waferstepper uses one of a number of commercially available techniques to generate alignment signals which indicate position relative to the wafer. The alignment signals are typically produced by optical measurement of alignment marks placed at appropriate locations on the wafer. A reticle is used to place the appropriately sized and shaped marks on a particular wafer process layer such that the marks can be readily identified by the waferstepper in subsequent processing steps. The reticle consists of a pattern which can be etched into the wafer using optical photolithography. Commonly used alignment mark types include Laser Step Alignment ("LSA"), Field Image Alignment ("FIA"), Laser Interferometric Alignment ("LIA"), Global Alignment Mark ("GAM"), and Global Alignment Mark LSA ("GAMLSA"), all developed by Nikon, and the Canon 6 Bar. Under current practice, a given test reticle will include only a single alignment mark type, even though wafersteppers can typically respond to a variety of alignment mark types. FIG. 1 illustrates two exemplary LSA alignment mark patterns for a Nikon waferstepper. The patterns consist of seven rows 10, 22 and seven columns 11, 23 of rectangles 12, 24.
The quality of the alignment marks is dependent upon how well the marks can be accurately translated into electrical signals understood by the waferstepper, which is a function of alignment mark size and shape. For example, in the LSA marks shown in FIG. 1, the quality of the alignment signal produced varies considerably depending upon the size of the elements making up the marks. In the Nikon waferstepper, a laser beam scans across the marks, and the diffracted light is detected to produce displays 14, 26 which consist of seven peaks 16, 28 indicative of position relative to the marks. In FIG. 1(a), the LSA mark shown produced the display 14 of seven peaks 16. The peaks shown are significantly clearer than the corresponding peaks 28 in display 26 of FIG. 1(b), produced in response to a laser scan of the mark including the larger rectangles 24. Use of the alignment signals in display 26 could lead to significant misalignment and thereby numerous device defects. It is therefore important that the parameters of an alignment mark be optimized for a particular application.
Registration is used to measure the accuracy of a process layer alignment performed using an alignment mark. Registration involves comparing the position of a subsequent layer to that of an existing layer by overlaying a distinct pattern on a matching pattern previously formed on the existing layer. The deviation in position of the overlay from the original provides a measure of accuracy of the alignment. Currently available registration structures include box-in-box, visual verniers, Automatic Measurement System ("AMS") and Canomap, each of which uses a different type of structure or pattern for comparison.
Under current practice, optimization of an alignment mark involves testing mark sizes and shapes by subsequent registration of test wafers to verify the accuracy of an alignment performed using the mark. One existing method to optimize an alignment mark uses a waferstepper test reticle with a single type of alignment mark to generate a first process layer, followed by printing the second layer resist pattern, and then performing registration on an overlay in both X and Y directions. The mark which results in the best registration reading is chosen as the optimal mark. However, this and other similar techniques have a number of disadvantages. The measurement results do not provide information as to the position of the alignment marks within acceptable process performance windows. A full array of alignment marks and registration overlays are not available to test. Standard overlay patterns for certain types of common registration techniques, such as box-in-box registration, are not available. Furthermore, previous layer process variations which may effect overlay are not taken into account in the measurements. In effect, none of the currently available techniques determine whether a particular alignment mark is indeed optimal.
In addition, in order to get overlay registration measurements from different alignment mark sizes, the test wafers would need to be stripped, respun and re-exposed several times, which could potentially alter the film surface and thereby affect alignment results. In order to optimize other types of alignment marks, a different set of test wafers would have to be generated using a different test reticle. Furthermore, the test reticles do not include the capability for orthogonal measurements, which means that measurement results are considerably more difficult to model mathematically. These drawbacks limit the achievable alignment accuracy, and result in significantly increased manufacturing costs and greater likelihood of device defects.
As is apparent from the above, there presently is a need for an improved test reticle and alignment mark optimization method which permits the use of a wide variety of alignment marks and registration overlay structures using a single test reticle and one set of test wafers. Previous layer process variations should be taken into account, and a window of acceptable alignment mark sizes produced. The capability for orthogonal measurements should be provided, thereby simplifying statistical analysis for determining the truly optimal mark size ranges for a given application. The test reticle and method should provide a suitable standard for optimal alignment mark optimization in many applications. Furthermore, the test reticle and method should be compatible with existing waferstepper alignment equipment and techniques.